Conventional legacy-based computer systems include a variety of peripheral and memory devices that communicate with the system's chip-set or processor via an Industry Standard Architecture (ISA) bus or an Expansion bus (X-bus). The system chip-set or processor must include a large amount of pins (e.g., approximately 50-70 pins) and associated circuitry to support the ISA bus or X-bus signals that are used to interface the chip-set or processor with legacy-based peripheral devices including input/output (I/O) or I/O controller devices such as parallel port controllers, serial port controllers, super I/O controllers, floppy disk controllers, keyboard controllers, and memory devices such as non-volatile memory devices that store, for example, basic input-output services (BIOS) information.
The large number of pins needed to support the ISA bus and X-bus standards generally increases overall system cost. For example, larger packages are required for a chip-set or processor. Larger pin-count packages generally cost more than smaller pin-count packages, and are generally more susceptible to manufacturing quality and reliability problems during package assembly and system integration processes. Furthermore, larger pin-count packages require a greater amount of surface area on a printed circuit board (PCB) on which a computer system may be implemented. Therefore, it would be desirable to replace the ISA bus or X-bus in a computer system with a bus that would support the same types of peripheral devices, but utilize a relatively smaller number of pins or signal lines.
The ISA bus and X-bus standards also limit the amount of memory or I/O address space to 24 bits or approximately 16 MBytes of memory or I/O address space. As some processors and chip-sets can support 32 bits or 64 bits of address space, aliasing has previously been required to translate the processor address space to the ISA address space. Aliasing can produce significant overhead such that the performance of the computer system may be negatively impacted. Therefore, it would be desirable to replace the ISA bus and X-bus standards with a bus that may support an address space that is compatible with the processor or chip-set address space, and that potentially is unlimited.
The ISA bus and X-bus standards have a further disadvantage of being asynchronous. This generally increases design complexity for components that need to generate and respond to ISA bus and X-bus signals. Therefore, it would be desirable to replace the ISA bus and X-bus standards with a bus that may support synchronous communication between components so as to generally reduce the complexity of the bus interface circuitry.